The LSI is manufactured by connecting basic constituent elements such as transistor, diode, capacitor, resistor, which are arranged electrically separately on a semiconductor substrate, via wirings.
The technology to connect the elements at a high density is the multi-layered wiring technology. This multi-layered wiring technology is the important technology that gets to determine the higher performance of the LSI. The parasitic effect of the resistance, the capacitor, etc. in the multi-layered wiring exerts a great influence on the circuit performance of the LSI.
From such viewpoint, the multi-layered wiring in which the copper (Cu) wiring having a low resistance and the interlayer insulating film formed of the material having a low dielectric constant are used in combination is now used. As this manufacturing method, the burying method, i.e., the so-called damascene method is employed.
The Cu wiring layer has such a characteristic that Cu contained in the Cu wiring layer is liable to diffuse into the interlayer insulating film, or the like during the annealing step, or the like. The Cu diffusion into the interlayer insulating film brings about disadvantages such that a leakage current in the interlayer insulating film is increased, etc. For this reason, the Cu wiring layer is formed in a wiring recess or a via in the interlayer insulating film via a barrier film.
FIG. 1 is a sectional view showing a part of steps of forming the multi-layered wiring by using the dual damascene method in the prior art. In the multi-layered wiring in the prior art, as shown in FIG. 1, first a first wiring layer 104 buried in a wiring recess 102a of a first interlayer insulating film 102, which is formed over a semiconductor substrate 100 onto which predetermined transistors, etc. are provided, is formed. The first wiring layer 104 is composed of a barrier film 104a and a first Cu film 104b, and is connected electrically to the transistors, etc. provided to the lower side.
Then, a second interlayer insulating film 106 consists of a silicon nitride film 106a and a silicon oxide film 106b is formed on the first wiring layer 104. Then, a wiring recess 106x is formed in the second interlayer insulating film 106 and then a via 106y that is communicated with this wiring recess is formed to expose the first wiring layer 104.
Then, a barrier film 108a is formed on an inner surface of the wiring recess 106x, an inner surface of the via 106y and the second interlayer insulating film 106. Then, a second Cu film 108b is formed via the seed Cu layer by the electroplating to fill the wiring recess 106x and the via 106y. 
Then, the second Cu film 108b and the barrier film 108a are polished by the CMP (Chemical Mechanical Polishing). Thus, a second wiring layer 108 consists of the barrier film 108a and the second Cu film 108b is formed in the wiring recess 106x and the via 106y. 
As the barrier film 108a formed in the wiring recess 106x and the via 106y, the transition metal or its nitride film such as tungsten (W) film, titanium (Ti) film, tantalum (Ta) film, or the like is used. Also, the barrier film 108a is formed by the sputter method to have a film thickness of about 10 to 30 nm. Because normally the sputter method has a poor step coverage, the barrier film 108a is formed thin on a side portion (S portion in FIG.1) of the via 106y, which has a high aspect ratio, rather than a bottom portion (B portion in FIG. 1) of the wiring recess 106x. 
As described above, in case the barrier film 108a is formed by the sputter method in the dual damascene method, such barrier film 108a is formed thin on the side portion S of the via 106y rather than the bottom portion B of the wiring recess 106x. In the barrier film 108a, the sufficient metal barrier property must be ensured over the entire inner surfaces of the wiring recess 106x and the via 106y. Therefore, the barrier film 108a must be formed to have the lowest minimum film thickness that can ensure the barrier property, on the side portion S of the via 106y at which the barrier film 108a has the thinnest film thickness. For this reason, the barrier film 108a having the unnecessarily thick film thickness is formed on the bottom portion B of the wiring recess 106x, etc. except the side portion S of the via 106y. 
Normally a resistance of the barrier film 108a made of the above material is considerably higher than a resistance of the second Cu film 108b serving as the major wiring layer. Then, since an overall thickness of the second wiring layer 108 is decided mainly by a depth of the wiring recess 106x, a film thickness of the second Cu film 108b becomes thin when a film thickness of the barrier film 108a becomes thick. Thus, an occupied rate of the barrier film 108a to the overall thickness of the second wiring layer 108 is increased. As a result, this leads an increase in a wiring resistance of the overall second wiring layer 108 (the barrier film 108a+the second Cu film 108b).
As a result, a delay of an electric signal that is propagated over the wiring in the multi-layered wiring of the LSI (wiring delay) is increased. In other words, this signifies that an increase in a CR time constant is caused in the electric circuit, and there is a problem that such delay is an obstacle to a high-speed (high-frequency) operation of the LSI.